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Connector pinout: PCI Express 4x PCI Express was introduced to overcome the limitations of the original PCI bus. Developed and released by Intel over a decade ago, the original PCI bus operated at 33MHz and 32 bits with a peak theoretical bandwidth of 132MB per second. It used a shared bus topology – bus bandwidth is shared among multiple devices - to enable communication among the different devices on the bus. PCI Express 1x - 64 pin Female Connector pin name direction description color 1B +12v +12 volt power 2 +12v +12 volt power 3 RSVD Reserved 4 GND Ground 5 SMCLK SMBus clock 6 SMDAT SMBus data 7 GND Ground 8 +3.3v +3.3 volt power 9 JTAG1 +TRST# 10 3.3Vaux 3.3v volt power 11 WAKE# Link Reactivation 12 RSVD Reserved 13 GND Ground 14 HSOp(0) Transmitter Lane 0, Differential pair 15 HSOn(0) 16 GND Ground 17 PRSNT#2 Hotplug detect 18 GND Ground 19 HSOp(1) Transmitter Lane 1, Differential pair 20 HSOn(1) 21 GND Ground 22 GND Ground 23 HSOp(2) Transmitter Lane 2, Differential pair 24 HSOn(2) 25 GND Ground 26 GND Ground 27 HSOp(3) Transmitter Lane 3, Differential pair 28 HSOn(0) 29 GND Ground 30 RSVD Reserved 31 PRSNT#2 Hot plug detect 32 GND Ground 1A PRSNT#1 Hot plug presence detect 2 +12v +12 volt power 3 +12v +12 volt power 4 GND Ground 5 JTAG2 TCK 6 JTAG3 TDI 7 JTAG4 TDO 8 JTAG5 TMS 9 +3.3v +3.3 volt power 10 +3.3v +3.3 volt power 11 PWRGD Power Good 12 GND Ground 13 REFCLK+ Reference Clock Differential pair 14 REFCLK- 15 GND Ground 16 HSIp(0) Receiver Lane 0, Differential pair 17 HSIn(0) 18 GND Ground 19 RSVD Reserved 20 GND Ground 21 HSIp(1) Receiver Lane 1, Differential pair 22 HSIn(1) 23 GND Ground 24 GND Ground 25 HSIp(2) Receiver Lane 2, Differential pair 26 HSIn(2) 27 GND Ground 28 GND Ground 29 HSIp(3) Receiver Lane 3, Differential pair 30 HSIn(3) 31 GND Ground 32 RSVD Reserved