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Connector pinout: ISA


ISA Connector





















pinnamedirectiondescriptioncolor
A1/I/O CH CKINI/O channel check; active low=parity error
A2D7IN/OUTData bit 7
A3D6IN/OUTData bit 6
A4D5IN/OUTData bit 5
A5D4IN/OUTData bit 4
A6D3IN/OUTData bit 3
A7D2IN/OUTData bit 2
A8D1IN/OUTData bit 1
A9D0IN/OUTData bit 0
A10I/O CH RDYINI/O Channel ready, pulled low to lengthen memory cycles
A11AENOUTAddress enable; active high when DMA controls bus
A12A19OUTAddress bit 19
A13A18OUTAddress bit 18
A14A17OUTAddress bit 17
A15A16OUTAddress bit 16
A16A15OUTAddress bit 15
A17A14OUTAddress bit 14
A18A13OUTAddress bit 13
A19A12OUTAddress bit 12
A20A11OUTAddress bit 11
A21A10OUTAddress bit 10
A22A9OUTAddress bit 9
A23A8OUTAddress bit 8
A24A7OUTAddress bit 7
A25A6OUTAddress bit 6
A26A5OUTAddress bit 5
A27A4OUTAddress bit 4
A28A3OUTAddress bit 3
A29A2OUTAddress bit 2
A30A1OUTAddress bit 1
A31A0OUTAddress bit 0
B1GNDGround
B2RESETOUTActive high to reset or initialize system logic
B3+5V+5 VDC
B4IRQ2INInterrupt Request 2
B5-5VDC-5 VDC
B6DRQ2INDMA Request 2
B7-12VDC-12 VDC
B8/NOWSINNo WaitState
B9+12VDC+12 VDC
B10GNDGround
B11/SMEMWOUTSystem Memory Write
B12/SMEMROUTSystem Memory Read
B13/IOWOUTI/O Write
B14/IOROUTI/O Read
B15/DACK3OUTDMA Acknowledge 3
B16DRQ3INDMA Request 3
B17/DACK1OUTDMA Acknowledge 1
B18DRQ1INDMA Request 1
B19/REFRESHIN/outRefresh
B20CLOCKOUTSystem Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
B21IRQ7INInterrupt Request 7
B22IRQ6INInterrupt Request 6
B23IRQ5INInterrupt Request 5
B24IRQ4INInterrupt Request 4
B25IRQ3INInterrupt Request 3
B26/DACK2OUTDMA Acknowledge 2
B27T/COUTTerminal count; pulses high when DMA term. count reached
B28ALEOUTAddress Latch Enable
B29+5V+5 VDC
B30OSCOUTHigh-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle)
B31GNDGround
C1SBHEIN/OUTSystem bus high enable (data available on SD8-15)
C2LA23IN/OUTAddress bit 23
C3LA22IN/OUTAddress bit 22
C4LA21IN/OUTAddress bit 21
C5LA20IN/OUTAddress bit 20
C6LA18IN/OUTAddress bit 18
C7LA17IN/OUTAddress bit 17
C8LA16IN/OUTAddress bit 16
C9/MEMRIN/OUTMemory Read (Active on all memory read cycles)
C10/MEMWIN/OUTMemory Write (Active on all memory write cycles)
C11SD08IN/OUTData bit 8
C12SD09IN/OUTData bit 9
C13SD10IN/OUTData bit 10
C14SD11IN/OUTData bit 11
C15SD12IN/OUTData bit 12
C16SD13IN/OUTData bit 13
C17SD14IN/OUTData bit 14
C18SD15IN/OUTData bit 15
D1/MEMCS16INMemory 16-bit chip select (1 wait, 16-bit memory cycle)
D2/IOCS16INI/O 16-bit chip select (1 wait, 16-bit I/O cycle)
D3IRQ10INInterrupt Request 10
D4IRQ11INInterrupt Request 11
D5IRQ12INInterrupt Request 12
D6IRQ13INInterrupt Request 13
D7IRQ14INInterrupt Request 14
D8/DACK0OUTDMA Acknowledge 0
D9DRQ0INDMA Request 0
D10/DACK5OUTDMA Acknowledge 5
D11DRQ5INDMA Request 5
D12/DACK6OUTDMA Acknowledge 6
D13DRQ6INDMA Request 6
D14/DACK7OUTDMA Acknowledge 7
D15DRQ7INDMA Request 7
D16+5 V
D17/MASTERINUsed with DRQ to gain control of system
D18GNDGround